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Freescale Semiconductor /MKE14Z7 /SIM /CHIPCTL

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Interpret as CHIPCTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)ADC_INTERLEAVE_EN 0 (00)CLKOUTDIV 0 (00)CLKOUTSEL 0 (0)PDB_BB_SEL 0 (00)PWTCLKSEL 0 (00)RTC32KCLKSEL

PDB_BB_SEL=0, ADC_INTERLEAVE_EN=00, PWTCLKSEL=00, CLKOUTSEL=00, CLKOUTDIV=00, RTC32KCLKSEL=00

Description

Chip Control register

Fields

ADC_INTERLEAVE_EN

ADC interleave channel enable

0 (00): No interleave channel
CLKOUTDIV

CLKOUT divider ratio

0 (00): Divided by 1

1 (01): Divided by 2

2 (10): Divided by 4

3 (11): Divided by 8
CLKOUTSEL

CLKOUT Select

0 (00): Reseved

1 (01): SCGCLKOUT(SIRC/FIRC/SOSC/LPFLL), see SCG_CLKOUTCNFG register.

2 (10): RTC oscillator (OSC32) clock (32 kHz)

3 (11): LPO clock (128 kHz)
PDB_BB_SEL

PDB back-to-back select

0 (0): PDB0 channel 0 back-to-back operation with ADC0 COCO[1:0] and PDB0 channel 1 back-to-back operation with ADC1 COCO[1:0]

1 (1): PDB0 Channel 0 back-to-back operation with COCO[0] of ADC0 and COCO[1] of ADC1 ; PDB0 Channel 1 back-to-back operation with COCO[0] of ADC1 and COCO[1] of ADC0
PWTCLKSEL

PWT clock source select

0 (00): PWT alternative clock is from the TCLK0 pin.

1 (01): PWT alternative clock is from the TCLK1 pin.

2 (10): PWT alternative clock is from the TCLK2 pin.
RTC32KCLKSEL

RTC 32K clock input select

0 (00): OSC32 clock output

1 (01): RTC_CLKIN

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data